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    • 专利摘要:
    A circuit for 3D ultrasound imaging systems (100) includes multiple sensor units (41), multiple unit circuits (31) and multiple row sharing circuits (32). The unit circuits (31) are connected with the sensor units (41) respectively. Each row of unit circuits (31) share a row sharing circuit (32). Each unit circuit (31) includes a first electrically controlled switch (311), a second electrically controlled switch (312) and a control circuit (313). Each row sharing circuit (32) includes a signal transmission bus (322), a signal receiving bus (323) and a row main control circuit (321). The signal transmission bus (322) and the signal receiving bus (323) of each row sharing circuit (32) extend through a corresponding row of unit circuits (31). The row main control circuit (321) of each row is configured to transmit a main control signal, a transmission control signal and a receiving control signal to a corresponding row of unit circuits (31).
    公开号:SE2030136A1
    申请号:SE2030136
    申请日:2020-04-24
    公开日:2020-10-26
    发明作者:Ying Liu
    申请人:Shenzhen Dansha Tech Co Ltd；
    IPC主号:
    专利说明:

    3D ULTRASOUND IMAGING SYSTEM Field of the Patent Application The present patent application generally relates to medical electronics and more specifically to a 3D ultrasound imaging system.
    Background A complete blood cell count is an important index of a blood test. Vascular imaging, especiallycardiovascular imaging, is often desired to illustrate as much as possible the shape,composition, physical Characteristics and other aspects of the atheromatous plaque in vesselssince this information is helpful for early diagnosis and interventional therapy of vasculardiseases. 2D ultrasound imaging systems are Widely applied in the above-mentioned diagnosis,but only images of a single location or images of a single plane can be obtained With suchmeans. ln addition, since the complex condition of 3D structures cannot be reflected in realtime, the real condition of vessels is often misjudged and therefore further diagnosis andtreatment is interfered or misled. Other means such as a computed tomography (CT)examination is harrnful to the human body and a nuclear magnetic resonance imaging (MRI)examination is relatively high in cost. Therefore, 3D ultrasound imaging systems With lowexamination costs and harrnlessness to the human body draw more and more attention of the public.
    A 3D ultrasound imaging system can provide 3D images in real time and realize accuratedetection of indexes such as the floW rate of blood in vessels, the development of atheromatousplaques and other indexes. HoWever, realizing 3D ultrasound imaging often requires a largenumber of ultrasound sensors and therefore leads to a large number of data channels and posesa challenge to the realization of large-scale integration of sensor modules and the design of 1 signal transceiver circuits. On the other hand, the practical requirements of 3D ultrasoundimaging for medical detection require that the usage position and direction of ultrasoundsensors should have stronger reconfigurability and should be fast switchable from multiplespecific and complex configuration schemes. A conventional 3D ultrasound imaging systemonly provides several optional and less complex schemes in this aspect and therefore restricts the application of the 3D ultrasound imaging system.
    Summary The present patent application is directed to a 3D ultrasound imaging system. In one aspect,the 3D ultrasound imaging system includes multiple sensor units, multiple unit circuitscorresponding to the multiple sensor units and connected with the multiple sensor unitsrespectively, and multiple row sharing circuits. Each unit circuit includes a first electricallycontrolled switch, a second electrically controlled switch and a control circuit. Each rowsharing circuit includes a signal transmission bus, a signal receiving bus and a row main controlcircuit. Each row of unit circuits share a row sharing circuit. The signal transmission bus andthe signal receiving bus of each row sharing circuit extend through a corresponding row ofunit circuits. The row main control circuit of each row is configured to transmit a main controlsignal, a transmission control signal and a receiving control signal to a corresponding row ofunit circuits. The first electrically controlled switch of each unit circuit is configured to controlwhether the corresponding sensor unit participates transmission of ultrasound signals. Thesecond electrically controlled switch of each unit circuit is configured to control whether thecorresponding sensor unit participates receiving of ultrasound signals. The control circuit ofeach unit circuit is a programmable logic control circuit configured to control switching of thefirst electrically controlled switch and the second electrically controlled switch of the sameunit circuit. The first electrically controlled switch of each unit circuit includes a first electronicswitch and a second electronic switch. The second electrically controlled switch of each unit circuit includes a third electronic switch and a fourth electronic switch. The control circuit of each unit Circuit includes a f1rst main control electronic switch, a second main control electronic switch, an AND gate chip, a diode, a capacitor, a f1rst inverter and a second inverter.
    The f1rst electronic switch, the second electronic switch, the third electronic switch, the fourthelectronic switch, the f1rst main control electronic switch and the second main controlelectronic switch may be N-type Metal-Oxide Semiconductor Field Effect Transistors, each may be including a gate electrode, a drain electrode and a source electrode.
    The drain electrode of the f1rst electronic switch may be connected with a corresponding sensorunit, the source electrode of the f1rst electronic switch may be connected with the drainelectrode of the second electronic switch and the gate electrode of the f1rst electronic switchmay be connected with the gate electrode of the second electronic switch. The source electrodeof the second electronic switch may be connected with the signal transmission bus. The sourceelectrode of the first main control electronic switch may be connected with the gate electrodeof the f1rst electronic switch, the drain electrode of the f1rst main control electronic switch mayreceive the transmission control signal and the gate electrode of the f1rst main control electronic switch may be connected with a reference voltage through the diode.
    The gate electrode of the f1rst main control electronic switch may be connected with the outputport of the AND gate chip through the capacitor. A f1rst input port of the AND gate chip mayreceive the main control signal and a second input port of the AND gate chip may receive the transmission control signal.
    The source electrode of the third electronic switch may be connected with the correspondingsensor unit, the drain electrode of the third electronic switch may be connected with the sourceelectrode of the fourth electronic switch and the gate electrode of the third electronic switchmay receive the transmission control signal through the f1rst inverter. The gate electrode of thefourth electronic switch may receive the receiving control signal and the drain electrode of the fourth electronic switch may be connected with the signal receiving bus. The drain electrode 3 of the second main control electronic switch may be connected with the signal receiving bus,the source electrode of the second main control electronic switch may be connected to theground and the gate electrode of the second main control electronic switch may receive the receiving control signal through the second inverter.
    The 3D ultrasound imaging system may further include a circuit board; multiple transceiverchips; and multiple sensor modules. The multiple transceiver chips may be integrated on thecircuit board and jointed sequentially, and thus forrning a matrix structure. The multiple sensormodules may be jointed sequentially and thus forrning a matrix structure and individually corresponding to the multiple transceiver chips.
    Each sensor module may be integrated on a corresponding transceiver chip respectively. Eachsensor module may include the multiple sensor units in an arrangement of a matrix. Eachtransceiver chip may include the multiple unit circuits in an arrangement of a matrix. At leastone transceiver chip of each row of transceiver chips may include the multiple row sharing circuits.
    In another aspect, the present patent application provides a 3D ultrasound imaging system. The3D ultrasound imaging system includes multiple sensor units, multiple unit circuitscorresponding to the multiple sensor units and connected with the multiple sensor unitsrespectively, and multiple row sharing circuits. Each unit circuit includes a first electricallycontrolled switch, a second electrically controlled switch and a control circuit. Each rowsharing circuit includes a signal transmission bus, a signal receiving bus and a row main controlcircuit. Each row of unit circuits share a row sharing circuit. The signal transmission bus andthe signal receiving bus of each row sharing circuit extend through a corresponding row ofunit circuits. The row main control circuit of each row is configured to transmit a main controlsignal, a transmission control signal and a receiving control signal to a corresponding row ofunit circuits. The first electrically controlled switch of each unit circuit is configured to control whether the corresponding sensor unit participates transmission of ultrasound signals. The 4 second electrically controlled switch of each unit circuit is configured to control whether thecorresponding sensor unit participates receiving of ultrasound signals. The control circuit ofeach unit circuit is a programmable logic control circuit configured to control switching of thefirst electrically controlled switch and the second electrically controlled switch of the sameunit circuit. The first electrically controlled switch of each unit circuit includes a first electronicswitch and a second electronic switch. The second electrically controlled switch of each unitcircuit includes a third electronic switch and a fourth electronic switch. The control circuit ofeach unit circuit includes a first main control electronic switch, a second main controlelectronic switch, an AND gate chip, a diode, a capacitor, a first inVerter and a second inVerter.The first electronic switch, the second electronic switch, the third electronic switch, the fourthelectronic switch, the first main control electronic switch and the second main controlelectronic switch are N-type Metal-Oxide Semiconductor Field Effect Transistors, eachincluding a gate electrode, a drain electrode and a source electrode. The drain electrode of thefirst electronic switch is connected with a corresponding sensor unit, the source electrode ofthe first electronic switch is connected with the drain electrode of the second electronic switchand the gate electrode of the first electronic switch is connected with the gate electrode of the second electronic switch.
    The source electrode of the second electronic switch is connected with the signal transmissionbus. The source electrode of the first main control electronic switch is connected with the gateelectrode of the first electronic switch, the drain electrode of the first main control electronicswitch receiVes the transmission control signal and the gate electrode of the first main controlelectronic switch is connected with a reference Voltage through the diode. The gate electrodeof the first main control electronic switch is connected with the output port of the AND gatechip through the capacitor. A first input port of the AND gate chip receiVes the main controlsignal and a second input port of the AND gate chip receiVes the transmission control signal.The source electrode of the third electronic switch is connected with the corresponding sensorunit, the drain electrode of the third electronic switch is connected with the source electrode of the fourth electronic switch and the gate electrode of the third electronic switch receiVes the transmission control signal through the first inverter. The gate electrode of the fourth electronicswitch receives the receiving control signal and the drain electrode of the fourth electronicswitch is connected with the signal receiving bus. The drain electrode of the second maincontrol electronic switch is connected with the signal receiving bus, the source electrode of thesecond main control electronic switch is connected to the ground and the gate electrode of thesecond main control electronic switch receives the receiving control signal through the second inverter.
    The 3D ultrasound imaging system may further include a circuit board; multiple transceiverchips; and multiple sensor modules. The multiple transceiver chips may be integrated on thecircuit board and jointed sequentially, and thus forrning a matrix structure. The multiple sensormodules may be jointed sequentially and thus forrning a matrix structure and individuallycorresponding to the multiple transceiver chips. Each sensor module may be integrated on acorresponding transceiver chip respectively. Each sensor module may include the multiplesensor units in an arrangement of a matrix. Each transceiver chip may include the multiple unitcircuits in an arrangement of a matrix. At least one transceiver chip of each row of transceiver chips may include the multiple row sharing circuits.
    Brief Description of the Drawings FIG. l is a top view of a 3D ultrasound imaging system in accordance with an embodiment of the present patent application.
    FIG. 2 is a cross-sectional view taken along the II-II line of the 3D ultrasound imaging system as depicted in FIG. 1.
    FIG. 3 illustrates the structure of a sensor module of the 3D ultrasound imaging system as depicted in FIG. 1.
    FIG. 4 illustrates the internal structure of half of the 3D ultrasound imaging system as depictedin FIG. 1.
    FIG. 5 illustrates a portion of the internal circuit of a transceiver chip of the 3D ultrasound imaging system as depicted in FIG. 1.
    FIG. 6 is a schematic circuit diagram of a unit circuit of the 3D ultrasound imaging system as depicted in FIG. 1.
    FIG. 7A illustrates the first selection mode of selecting sensor units of the 3D ultrasoundimaging system as depicted in FIG. 1.
    FIG. 7B illustrates the second operating mode of selecting sensor units of the 3D ultrasound imaging system as depicted in FIG. 1.
    FIG. 7C and FIG. 7D illustrate the third operating mode of selecting sensor units of the 3D ultrasound imaging system as depicted in FIG. 1.
    Detailed Description Reference will now be made in detail to a preferred embodiment of the 3D ultrasound imagingsystem disclosed in the present patent application, examples of which are also provided in thefollowing description. Exemplary embodiments of the 3D ultrasound imaging systemdisclosed in the present patent application are described in detail, although it will be apparentto those skilled in the relevant art that some features that are not particularly important to an understanding of the 3D ultrasound imaging system may not be shown for the sake of clarity.
    Furthermore, it should be understood that the 3D ultrasound imaging system disclosed in the present patent application is not limited to the precise embodiments described below and that 7 various changes and modifications thereof may be effected by one skilled in the art Withoutdeparting from the spirit or scope of the protection. For example, elements and/or features ofdifferent illustrative embodiments may be combined With each other and/or substituted for each other Within the scope of this disclosure.
    FIG. 1 is a top view of a 3D ultrasound imaging system in accordance With an embodiment ofthe present patent application. Referring to FIG. 1, the 3D ultrasound imaging system 100 inaccordance With an embodiment of the present patent application includes an outer housing 10, a circuit board 20, multiple transceiver chips 30 and multiple sensor modules 40.
    Referring to FIG. 2, the outer housing 10 is made of conductive materials (e. g. aluminum) andcapable of being connected to the ground so as to resist electromagnetic interference. In thisembodiment, the outer housing 10 is covering over the circuit board 20 so that anaccommodating cavity is formed and configured to accommodate the multiple transceiver chips 30 and the multiple sensor modules 40.
    In this embodiment, the outer housing 10 is jointly formed by tWo symmetrical parts. In other embodiments, the outer housing 10 can be a unibody structure.
    The multiple transceiver chips 30 are integrated on the circuit board 20 and jointed sequentially,thus forming a matrix structure. The circuit board 20 is configured to electrically connect each electronic component in the transceiver chip 30.
    In this embodiment, the multiple transceiver chips 30 are formed into a matrix With 12 roWsand 2 columns so as to reduce the size of the 3D ultrasound imaging system 100. Of course,the roWs and columns of the matrix structure are not limited to the roWs and columns in thisembodiment and can be determined according to requirements. In other embodiments, themultiple transceiver chips 30 can also be j ointed into a non-matrix according to requirements (e.g. shapes of the Chinese characters Hr” and “åfåfi etc.). 8 In this embodiment, the Circuit board 20 is j ointly formed by two symmetrical parts and eachcolumn of transceiver chips 30 are integrated on one of the two parts. In other embodiments, the circuit board 20 can be a unibody structure.
    The multiple sensor modules 40 are integrated on the multiple transceiver chips 30 andindividually corresponding to the multiple transceiver chips 30. Each sensor module 40 isintegrated on a corresponding transceiver chip 30 and connected with the correspondingtransceiver chip 30. The multiple sensor modules 40 are sequentially j ointed and thus forrning a matrix structure.
    Referring to FIG. 3, each sensor module 40 includes multiple sensor units 41. In thisembodiment, the multiple sensor units 41 are sequentially j ointed into a matrix structure so asto reduce the size of the 3D ultrasound imaging system 100. In this embodiment, each sensor unit 41 includes a piezoelectric sensor.
    Referring to FIG. 4, each transceiver chip 30 includes multiple unit circuits 31 in an arrangement of a matrix and multiple row sharing circuits 32.
    The multiple unit circuits 31 are individually corresponding to the multiple sensor units 41 andeach unit circuit 31 is connected with a corresponding sensor unit 41. In this embodiment, eachunit circuit 31 is connected with a corresponding sensor unit 41 through a metal ball 301 and a metal pad 302.
    Referring to FIG. 5, each unit circuit 31 includes a first electrically controlled switch 311, a second electrically controlled switch 312 and a control circuit 313.
    The first electrically controlled switch 311 is configured to control whether the corresponding sensor unit 41 participates transmission of ultrasound signals. The second electrically 9 controlled switch 312 is configured to control whether the corresponding sensor unit 41participates receiVing of ultrasound signals. The control circuit 313 is configured to control theswitching of the first electrically controlled switch 311 and the second electrically controlledswitch 312. ln this embodiment, the control circuit 313 is a programmable logic control circuitincluding a unit programmable memory. The unit programmable memory includes multipleshift registers and each shift register includes multiple flip-flops. The unit programmablememory is conf1gured to fast select sensor units 41 which participate transmission or receiVing of ultrasound signals.
    Each row sharing circuit 32 is corresponding to a row of unit circuits 31 and configured to transmit control signals to the corresponding row of unit circuits 31.
    The row sharing circuit 32 includes a row main control circuit 321, a signal transmission bus 322 and a signal receiVing bus 323.
    The signal transmission bus 322 and the signal receiVing bus 323 extend through acorresponding row of unit circuits 31. The row main control circuit 321 of each row isconfigured to receive an extemal main control signal (DX, an extemal transmission controlsignal Tx-EN and an extemal receiVing control signal Rx-EN (referring to FIG. 6) from aprocessor of the 3D ultrasound imaging system 100 and transmit the main control signal<ï> x,the transmission control signal Tx-EN and the receiVing control signal Rx-EN to the multiplecontrol circuits 313. Referring to FIG. 5, the unit circuits 31 which the signal transmission busTX (i) or the signal receiVing bus Rx (i) extends through reside in the ith row of the matrix of the unit circuits.
    Specifically, the first electrically controlled switch 311 is configured to control the conductingstate between the corresponding sensor unit 41 and the signal transmission bus Tx(i), so as tocontrol whether the corresponding sensor unit 41 participates transmission of ultrasound signals. The second electrically controlled switch 312 is configured to control the conducting state between the corresponding sensor unit 41 and the signal receiving bus Rx(i), so as to control Whether the corresponding sensor unit 41 participates receiving of ultrasound signals. ln addition, each row sharing circuit 32 further includes a driver circuit 324 and a low-noiseamplifier 325 which are sitting on the signal receiving bus Rx (i). The driver circuit 324 isconnected with the multiple unit circuits 3l through the low-noise amplifier 325. The low-noise amplifier 325 is configured to amplify signals on the signal receiving bus Rx(i). Thedriver circuit 324 is configured to further amplify the output of the low-noise amplifier 325 and transmit the signals amplified by the driver circuit 324 to the row main control circuit 32l.
    Referring to FIG. 6, in this embodiment, the first electrically controlled switch 3ll includes afirst electronic switch 3l la, a second electronic switch 3l lb and a voltage regulator module.The second electrically controlled switch 3l2 includes a third electronic switch 3l2a and afourth electronic switch 3 l2b. The control circuit 3 l3 includes a first main control electronicswitch 3l3a, a second main control electronic switch 3l3b, an AND gate chip 3l3c, a diode3 l3d, a capacitor 3 l3e, a first inverter 3l3f and a second inverter 3l3g.
    The first electronic switch 3 l la, the second electronic switch 3 l lb, the third electronic switch3l2a, the fourth electronic switch 3l2b, the first main control electronic switch 3l3a and thesecond main control electronic switch 3l3b are N-type Metal-Oxide Semiconductor Field Effect Transistors, each including a gate electrode, a drain electrode and a source electrode.
    The drain electrode of the first electronic switch 3l la is connected with a corresponding sensorunit E (i, j) (i.e. the sensor unit disposed in the ith row and the jth column), the source electrodeof the first electronic switch 3 l la is connected with the drain electrode of the second electronicswitch 3 l lb while the gate electrode of the first electronic switch 3l la is connected with thegate electrode of the second electronic switch 3 l lb. The source electrode of the second electronic switch 3 l lb is connected with the signal transmission bus Tx (i). 11 The source electrode of the first main control electronic switch 3 l3a is connected with the gateelectrode of the first electronic switch 3lla; the drain electrode of the first main controlelectronic switch 3l3a receiVes the transmission control signal Tx-EN; the gate electrode ofthe first main control electronic switch 3l3a is connected with a reference Voltage VDDthrough the diode 3 l3d; the positive electrode of the diode 3 l3d is connected with the referenceVoltage VDD while the negative electrode of the diode 3l3d is connected with the gateelectrode of the first main control electronic switch 3 l3a. The gate electrode of the first maincontrol electronic switch 3 l3a is connected with the output port of the AND gate chip 3l3cthrough the capacitor 3l3e. A first input port of the AND gate chip 3 l3c receiVes the main control signal (D x and a second input port of the AND gate chip 3 l3c receiVes the transmission control signal Tx-EN.
    The source electrode of the third electronic switch 3 l2a is connected with the correspondingsensor unit E (i, j ); the drain electrode of the third electronic switch 3 l2a is connected with thesource electrode of the fourth electronic switch 3 l2b; the gate electrode of the third electronicswitch 3 l2a receiVes the transmission control signal Tx-EN through the first inVerter 3 l3f Theoutput port of the first inVerter 3 l 3f is connected with the gate electrode of the third electronicswitch 3l2a; the input port of the first inVerter 3l3f receiVes the transmission control signalTx-EN. The gate electrode of the fourth electronic switch 3 l2b receiVes the receiving controlsignal Rx-EN; the drain electrode of the fourth electronic switch 3l2b is connected with the signal receiving bus Rx (i).
    The drain electrode of the second main control electronic switch 3l3b is connected with thesignal receiving bus Rx (i); the source electrode of the second main control electronic switch3 l3b is connected to the ground; the gate electrode of the second main control electronic switch3 l3b receiVes the receiving control signal Rx-EN through the second inVerter 3 l 3 g. The inputport of the second inVerter 3l3g receives the receiving control signal Rx-EN and the outputport of the second inVerter 3 l3 g is connected with the gate electrode of the second main control electronic switch 3 l3b. 12 Further, the first electrically controlled switch 311 further includes the voltage regulatormodule configured to keep the voltage between the gate electrode and the source electrode ofthe first electronic switch 31 la constant, so as to protect the first electronic switch 31 la andprevent the first electronic switch 3lla from breaking down because of an excessively hightransient voltage between the gate electrode and the source electrode of the first electronicswitch 311a. The voltage regulator module includes a voltage regulating diode 31lc and avoltage regulating capacitor 31 ld. The positive electrode of the voltage regulating diode 31 lcis connected with the source electrode of the first electronic switch 31 la; the negative electrodeof the voltage regulating diode 31 lc is connected with the gate electrode of the first electronicswitch 311a. The voltage regulating capacitor 31ld is connected in parallel with the voltage regulating diode 31 lc.
    The operating process of the unit circuit 31 is as follows: (1) When the sensor unit E (i, j) isselected to transmit ultrasound signals, the transmission control signal Tx-EN is set as a highlevel “1” and the main control signal (DX is set as a high level “1”, and therefore the outputport of the AND gate chip 3l3c outputs a high level “l”. The voltage of the gate electrode ofthe first main control electronic switch 3 l3a is increased to a value greater than the referencevoltage VDD, so that the signal at the gate electrode of the first main control electronic switch3l3a changes to a high level “l” and the drain electrode and the source electrode of the firstmain control electronic switch 3 l3a are conducted. At this time, the gate electrode of the firstelectronic switch 31 la and the gate electrode of the second electronic switch 31 lb receive thetransmission control signal Tx-EN and signals at the gate electrodes of the first electronicswitch 311a and the second electronic switch 31 lb change to a high level “1”, and thereforethe drain electrode of the first electronic switch 31 la are conducted to the source electrode ofthe first electronic switch 31 la while the drain electrode of the second electronic switch 31 lbare conducted to the source electrode of the second electronic switch 31 lb, so that the sensorunit E (i, j) is connected with the signal transmission bus TX (i). Since the transmission control signal Tx-EN is a high level “l” at this moment, the output port of the first inverter 313foutputs 13 a low level “0”, so that the signal at the gate electrode of the third electronic switch 312a is alow level, the drain electrode and the source electrode of the third electronic switch 312a aredisconnected while the sensor unit E (i, j) and the signal receiving bus Rx (i) are disconnected.As a result, the sensor unit E (i, j) cannot receive ultrasound signals at this moment. In otherwords, when the sensor unit E (i, j) transmits ultrasound signals, the sensor unit E (i, j) cannotreceive ultrasound signals. And vice versa, when the sensor unit E (i, j) is selected to receiveultrasound signals, the receiving control signal Rx-EN is set as a high level “1” and thetransmission control signal Tx-EN is set as a low level “0” and therefore cannot transmit ultrasound signals.
    In addition, when the sensor unit E (i, j) is not selected to receive ultrasound signals butselected only to transmit ultrasound signals, the receiving control signal Rx-EN is set as a lowlevel “0”, so that the drain electrode and the source electrode of the fourth electronic switch312b are disconnected. At this time, the second inverter 313 g receives the receiving controlsignal Rx-EN and outputs a high level “1” while the signal at the gate electrode of the secondmain control electronic switch 313b changes to a high level “1”, so that the drain electrode andthe source electrode of the second main control electronic switch 313b are conducted.Therefore, the signal receiving bus Rx (i) is connected to the ground and signals of unselected sensor units E (i, j) are effectively prevented from coupling into the signal receiving bus Rx (i).
    In this embodiment, the first electronic switch 31 la and the second electronic switch 31 lb areHigh voltage Lateral Double-Diffused Metal-Oxide-Semiconductor field effect transistors.The peak voltage of the signal transmission bus Tx (i) is 30V. Since the first electricallycontrolled switch 311 in the present patent application includes two electronic switches (i.e.the first electronic switch 311a and the second electronic switch 311b), signal attenuationproduced by capacitive load can be effectively reduced while the first electrically controlled switch 311 is not affected even if there is a short circuit between two adjacent sensor units 41 14 because of manufacturing defects. Compared with circuits consisting of latches, the circuit of the present patent application is more compact and therefore helps to save area and integrate.
    In this embodiment, the structures of transceiver chips 30 in a same row are identical. In atransceiver chip 30, each row of unit circuits 31 share a same row sharing circuit 32, a samesignal transmission bus Tx (i) and a same signal receiving bus Rx (i) and occupy a data channel,so that the number of data channel is not too big even if the sensor module 40 integrates in alarge scale . For example, each row of unit circuits 31 in the transceiver chip 30 include n unit circuits 31 and the n unit circuits 31 share a row sharing circuit 32.
    In other embodiments, the structures of transceiver chips 30 in a same row can be different andonly one transceiver chip 30 in each row of transceiver chips 30 is required to have multiplerow sharing circuits 32. The signal transmission buses Tx(i) and the signal receiving busesRx(i) of the multiple row sharing circuits 32 extend through other transceiver chips 30 withoutrow sharing circuits 32, so that other transceiver chips 30 can receive control signals fromcorresponding row sharing circuits 32. For example, if the number of transceiver chips 30 in arow of transceiver chips 30 is a while a row of unit circuits 31 in each transceiver chip 30 include n unit circuits 31, then a >< n unit circuits 31 share one row sharing circuit 32.
    The multiple row sharing circuits 32 can transmit control instructions so as to selectcorresponding sensor units 41 to transmit or receive ultrasound signals. Sensor units 41 selected to transmit or receive ultrasound signals are formed into a pattem.
    It is understood that according to different requirements of medical imaging, users expect thatthe 3D ultrasound imaging system has different operating modes for users to select as required,and in other words, to realize reconfigurability of operating modes. Specifically, two schemesare taken as an example. Scheme A is selecting all sensor units 41 in a column at a time andthen selecting a next adjacent column of sensor units 41. Suppose there are 10 columns of target sensor units 41, then ten images need to be transmitted 10 times and the 10 images are synthesized so that the image resolution of the synthesized image is high and the details areclear but it is relatively time-consuming (e. g. it takes 0.1 second to transmit image signals forone time and therefore it takes 1 second to produce a complete image) and the time resolutionis relatively low. Scheme B is selecting all sensor units 41 at a time so that the image needs tobe transmitted only once, which saves much time (it takes only 0.1 second to produce acomplete image). However, the details of such an image, which is taken by one time, are lessclear than the details of images produced by scheme A and the spatial resolution is relativelylow, which has the effect of “exchanging spatial resolution for time resolution”. In the practicaloperating process, if users have relatively high requirements for spatial resolution, scheme A is adopted; if users have relatively high requirements for time resolution, scheme B is adopted.
    Of course, in the practical operating process, if users only need to acquire images of someparticular locations, the usage position and direction of the multiple sensor modules 40 needto be configured, and therefore some sensor units 41 must be selected as target sensor units foroperating while other sensor units 41 do not operate. The multiple row sharing circuits 32 have the following three operating modes.
    The first operating mode: referring to FIG. 4 and FIG. 7A, the multiple row sharing circuits 32operate sequentially; after the row sharing circuit 32 of the first row selects a target sensor unit411 from the corresponding row (i.e. the first row) of sensor units 41, the row sharing circuit32 of the second row begins to select a target sensor unit 421 from the corresponding row ofsensor units 41. The process goes on until all row sharing circuits 32 finish selecting the target sensor units for the corresponding rows.The second operating mode: referring to FIG. 7B, the multiple row sharing circuits 32 operate simultaneously and select sensor units in a predeterrnined column (e. g. the Pth column) from the sensor units 41 in all corresponding rows as the target sensor units 431. 16 The third operating mode: referring to FIG. 7C, the multiple row sharing circuits 32 operatesimultaneously and each row sharing circuit 32 first selects a sensor unit 41 from thecorresponding row of sensor units 41 as a preset sensor unit 441; then referring to FIG. 7D,the multiple row sharing circuits 32 operate simultaneously and each row sharing circuit 32selects a sensor unit 41 adjacent to the preset sensor unit by one or multiple columns from the corresponding row of sensor units 41 as the target sensor unit 451.
    Users can select a required operating mode according to practical medical requirements ofultrasound detection, which effectively realizes the reconfigurability of operating modes,greatly reduces the time period for selecting sensor units 41 and effectively improves the operating efficiency.
    Compared with conventional 3D ultrasound imaging systems, the 3D ultrasound imagingsystem of the present patent application forms a large sensor matrix through jointing multiplesensor modules, and is applicable to systems with large scale integrated sensors. At the sametime, since at least one of transceiver chips in a same row has multiple row sharing circuits,each row of unit circuits share a row sharing circuit, so that the number of data channel is nottoo big even if the large scale sensor modules are integrated. Besides, row sharing circuits haveavoided repeating configuring some circuits (e. g. low-noise amplifier) in each unit circuit, sothat the unit circuits are more compact, which helps to improve the density of integration. Inaddition, diverse and fast selection of required sensor units can be realized by configuring aunit programmable memory in the control circuit of each unit circuit, so that the usage positionand direction of the multiple sensor modules have stronger reconfigurability and can be fastswitchable from multiple specific and complex configuration schemes and therefore the operating efficiency is effectively improved.
    While the present patent application has been shown and described with particular referencesto a number of embodiments thereof, it should be noted that various other changes or modifications may be made without departing from the scope of the present invention. 17
    权利要求:
    Claims (10)
    [1] 1. A 3D u1trasound imaging system (100) comprising: a p1ura1ity of sensor units (41); a p1ura1ity of unit circuits (31) corresponding to the p1ura1ity of sensor units (41) and connectedwith the p1ura1ity of sensor units (41) respectively, each unit circuit (31) comprising a firste1ectrica11y contro11ed switch (311), a second e1ectrica11y contro11ed switch (312) and a contro1circuit (313); and a p1ura1ity of row sharing circuits (32), each row sharing circuit (32) comprising a signaltransmission bus (322), a signal receiving bus (323) and a row main contro1 circuit (321), eachrow of unit circuits (31) sharing a row sharing circuit (32); wherein: the signa1 transmission bus (322) and the signa1receiVing bus (323) of each row sharing circuit(32) extend through a corresponding row of unit circuits (31); the row main contro1 circuit (321) of each row is configured to transmit a main contro1 signa1,a transmission contro1 signa1 and a receiving contro1 signa1 to a corresponding row of unitcircuits (31); the first e1ectrica11y contro11ed switch (311) of each unit circuit (31) is configured to contro1whether the corresponding sensor unit (41) participates transmission of u1trasound signa1s;the second e1ectrica11y contro11ed switch (312) of each unit circuit (31) is configured to contro1whether the corresponding sensor unit (41) participates receiving of u1trasound signa1s; the contro1 circuit (313) of each unit circuit (31) is a programmab1e 1ogic contro1 circuitconfigured to contro1 switching of the first e1ectrica11y contro11ed switch (311) and the seconde1ectrica11y contro11ed switch (312) of the same unit circuit (31); the first e1ectrica11y contro11ed switch (31 1) of each unit circuit (31) comprises a first e1ectronicswitch (311a) and a second e1ectronic switch (311b); the second e1ectrica11y contro11ed switch (312) of each unit circuit (31) comprises a thirde1ectronic switch (312a) and a fourth e1ectronic switch (312b); and 18 the control Circuit (313) of each unit circuit (31) comprises a first main control electronicswitch (313a), a second main control electronic switch (3l3b), an AND gate chip (313c), adiode (313d), a capacitor (313e), a first inverter (313f) and a second inverter (3 13 g).
    [2] 2. The 3D ultrasound imaging system (100) of claim 1, wherein the first electronic switch(311a), the second electronic switch (311b), the third electronic switch (312a), the fourthelectronic switch (312b), the first main control electronic switch (313a) and the second maincontrol electronic switch (313b) are N-type Metal-Oxide Semiconductor Field Effect Transistors, each comprising a gate electrode, a drain electrode and a source electrode.
    [3] 3. The 3D ultrasound imaging system (100) of claim 2, wherein the drain electrode of the firstelectronic switch (311a) is connected with a corresponding sensor unit (41), the sourceelectrode of the first electronic switch (311a) is connected with the drain electrode of thesecond electronic switch (31 lb) and the gate electrode of the first electronic switch (311a) isconnected with the gate electrode of the second electronic switch (311b); the source electrodeof the second electronic switch (31 lb) is connected with the signal transmission bus (322); thesource electrode of the first main control electronic switch (313a) is connected with the gateelectrode of the first electronic switch (311a), the drain electrode of the first main controlelectronic switch (313a) receiVes the transmission control signal and the gate electrode of thefirst main control electronic switch (313a) is connected with a reference Voltage through the diode (313a).
    [4] 4. The 3D ultrasound imaging system (100) of claim 3, wherein the gate electrode of the firstmain control electronic switch (313a) is connected with the output port of the AND gate chip(313c) through the capacitor (313e); a first input port of the AND gate chip (313c) receiVes themain control signal and a second input port of the AND gate chip (313c) receiVes the transmission control signal. 19
    [5] 5. The 3D ultrasound imaging system (100) of claim 3, wherein the source electrode of thethird electronic switch (3l2a) is connected with the corresponding sensor unit (4l), the drainelectrode of the third electronic switch (3l2a) is connected with the source electrode of thefourth electronic switch (3l2b) and the gate electrode of the third electronic switch (3l2a)receives the transmission control signal through the first inverter (3 l3f); the gate electrode ofthe fourth electronic switch (3 l2b) receives the receiving control signal and the drain electrodeof the fourth electronic switch (3 l2b) is connected with the signal receiving bus (323); and thedrain electrode of the second main control electronic switch (3 l3b) is connected with the signalreceiving bus (323), the source electrode of the second main control electronic switch (3l3b)is connected to the ground and the gate electrode of the second main control electronic switch (3 l3b) receives the receiving control signal through the second inverter (3 l3 g).
    [6] 6. The 3D ultrasound imaging system (l00) of claim 5 further comprising a circuit board (20);a plurality of transceiver chips (30); and a plurality of sensor modules (40), wherein theplurality of transceiver chips (30) are integrated on the circuit board (20) and jointedsequentially, and thus forrning a matrix structure; the plurality of sensor modules (40) arejointed sequentially and thus forrning a matrix structure and individually corresponding to the plurality of transceiver chips (30).
    [7] 7. The 3D ultrasound imaging system (l00) of claim 6, wherein each sensor module (40) isintegrated on a corresponding transceiver chip (30) respectively; each sensor module (40)comprises the plurality of sensor units (4l) in an arrangement of a matrix; each transceiver chip (3 0) comprises the plurality of unit circuits (3 l) in an arrangement of a matrix.
    [8] 8. The 3D ultrasound imaging system (l00) of claim 7, wherein at least one transceiver chip (3 0) of each row of transceiver chips (3 0) comprises the plurality of row sharing circuits (32).
    [9] 9. A 3D ultrasound imaging system (l00) comprising: a plurality of sensor units (4l); a plurality of unit circuits (31) corresponding to the plurality of sensor units (41) and connectedwith the plurality of sensor units (41) respectively, each unit circuit (31) comprising a firstelectrically controlled switch (311), a second electrically controlled switch (312) and a controlcircuit (313); and a plurality of row sharing circuits (32), each row sharing circuit (32) comprising a signaltransmission bus (322), a signal receiVing bus (323) and a row main control circuit (321), eachrow of unit circuits (31) sharing a row sharing circuit (32); wherein: the signal transmission bus (322) and the signal receiving bus (323) of each row sharing circuit(32) extend through a corresponding row of unit circuits (31); the row main control circuit (321) of each row is configured to transmit a main control signal,a transmission control signal and a receiVing control signal to a corresponding row of unitcircuits (31); the first electrically controlled switch (311) of each unit circuit (31) is configured to controlwhether the corresponding sensor unit (41) participates transmission of ultrasound signals;the second electrically controlled switch (312) of each unit circuit (31) is configured to controlwhether the corresponding sensor unit (41) participates receiVing of ultrasound signals; the control circuit (313) of each unit circuit (31) is a programmable logic control circuitconfigured to control switching of the first electrically controlled switch (311) and the secondelectrically controlled switch (312) of the same unit circuit (31); the first electrically controlled switch (31 1) of each unit circuit (31) comprises a first electronicswitch (31 la) and a second electronic switch (311b); the second electrically controlled switch (312) of each unit circuit (31) comprises a thirdelectronic switch (312a) and a fourth electronic switch (312b); the control circuit (313) of each unit circuit (31) comprises a first main control electronicswitch (313a), a second main control electronic switch (313b), an AND gate chip (313c), adiode (313d), a capacitor (313e), a first inverter (313f) and a second inverter (313g); the first electronic switch (311a), the second electronic switch (311b), the third electronicswitch (312a), the fourth electronic switch (312b), the first main control electronic switch (313a) and the second main control electronic switch (313b) are N-type Metal-Oxide 21 Semiconductor Field Effect Transistors, each comprising a gate electrode, a drain electrodeand a source electrode; the drain electrode of the first electronic switch (3lla) is connected with a correspondingsensor unit (41), the source electrode of the first electronic switch (3 l la) is connected with thedrain electrode of the second electronic switch (3llb) and the gate electrode of the firstelectronic switch (3 l la) is connected with the gate electrode of the second electronic switch(3 l lb); the source electrode of the second electronic switch (3l lb) is connected with the signaltransmission bus (322); the source electrode of the first main control electronic switch (3l3a) is connected with thegate electrode of the first electronic switch (3l la), the drain electrode of the first main controlelectronic switch (3 l3a) receiVes the transmission control signal and the gate electrode of thefirst main control electronic switch (3l3a) is connected with a reference Voltage through thediode (3 l3d); the gate electrode of the first main control electronic switch (3 l3a) is connected with the outputport of the AND gate chip (3 l3c) through the capacitor (3 l3e); a first input port of the AND gate chip (3l3c) receiVes the main control signal and a secondinput port of the AND gate chip (3 l 3c) receiVes the transmission control signal; the source electrode of the third electronic switch (3 l2a) is connected with the correspondingsensor unit (4l), the drain electrode of the third electronic switch (3 l2a) is connected with thesource electrode of the fourth electronic switch (3l2b) and the gate electrode of the thirdelectronic switch (3l2a) receiVes the transmission control signal through the first inVerter(3 l3 f); the gate electrode of the fourth electronic switch (3 l2b) receiVes the receiVing control signaland the drain electrode of the fourth electronic switch (3l2b) is connected with the signalreceiVing bus (323); and the drain electrode of the second main control electronic switch (3 l3b) is connected with the signal receiving bus (323), the source electrode of the second main control electronic switch 22 (3 l3b) is connected to the ground and the gate electrode of the second main control electronic switch (3 l3b) receives the receiving control signal through the second inverter (3 l3 g).
    [10] 10. l0. The 3D ultrasound imaging system of claim l further comprising a circuit board (20), aplurality of transceiver chips (3 0) and a plurality of sensor modules (40), wherein the pluralityof transceiver chips (3 0) are integrated on the circuit board (20) and j ointed sequentially, andthus forrning a matrix structure; the plurality of sensor modules (40) are j ointed sequentiallyand thus forrning a matrix structure and individually corresponding to the plurality oftransceiver chips (30); each sensor module (40) is integrated on a corresponding transceiverchip (30) respectively; each sensor module (40) comprises the plurality of sensor units (41) inan arrangement of a matrix; each transceiver chip (3 0) comprises the plurality of unit circuits(3 l) in an arrangement of a matrix; at least one transceiver chip (3 0) of each row of transceiver chips (30) comprises the plurality of row sharing circuits (32). 23
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    SE1930136|2019-04-25|
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